View LT4430_424885.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT4430 Secondary-Side Optocoupler Driver FEATURES

DESCRIPTIO

600mV Reference (1.25% Over Temperature) Wide Input Supply Range: 3V to 20V Overshoot Control Function Prevents Output Overshoot on Startup and Short-Circuit Recovery High Bandwidth Error Amplifier Permits Simple Loop Frequency Compensation Ground-Referenced OptoCoupler Drive 10mA OptoCoupler Drive with Current Limiting Low Profile (1mm) ThinSOTTM Package
The LT(R)4430 drives the optocoupler that crosses the galvanic barrier in an isolated power supply. The IC contains a precision-trimmed reference, a high bandwidth error amplifier, an inverting gain of 6 stage to drive the optocoupler and unique overshoot control circuitry. The LT4430's 600mV reference provides 0.75% initial accuracy and 1.25% tolerance over temperature. A high bandwidth 9MHz error amplifier permits simple frequency compensation and negligible phase shift at typical loop crossover frequencies. The optocoupler driver provides 10mA of output current and is short-circuit protected. A unique overshoot control function prevents output overshoot on startup and short-circuit recovery with a single capacitor. The LT4430 is available in the low profile 6-lead SOT-23 package.
, LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
APPLICATIO S

48V Input Isolated DC/DC Converters Isolated Telecommunication Power Systems Distributed Power Step-Down Converters Offline Isolated Power Supplies Industrial Control Systems Automotive and Heavy Equipment
TYPICAL APPLICATIO
ISOLATION BARRIER VIN
Simplified Isolated Synchronous Forward Converter Isolated Flyback Telecom Converter Startup with Overshoot Control (See Schematic on Page 20)
VIN 50V/DIV LT1952 FG CG SYNC LTC3900 VCC
+
*
*
+
VOUT
* *
VCC
VIN GND OC LT4430
OPTO COMP FB
VOUT 5V/DIV OVERSHOOT CONTROL IMPLEMENTED t = 5ms/DIV
4430 TA01b
4430 TA01
U
4430f
U
U
1
LT4430 ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW VIN 1 GND 2 OC 3 6 OPTO 5 COMP 4 FB
Supply Voltage VIN ........................................................................20V FB Voltage .................................................... -0.3V to 6V OPTO Short-Circuit Duration ............................ Indefinite Operating Junction Temperature Range (Note 2) .......................................................... -40C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
LT4430ES6 S6 PART MARKING LTBFY
S6 PACKAGE 6-LEAD PLASTIC SOT-23 TJMAX = 125C, JA = 250C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VIN IIN VUVLO VFB PARAMETER Input Voltage Range Supply Current Undervoltage Lockout Threshold Feedback Reference Voltage
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 5V, FB = VFB, COMP = 1V, unless otherwise noted (Note 3).
CONDITIONS
MIN 3

TYP 1.9
MAX 20 3.9 2.5 0.6045 0.6075 0.1 -5
UNITS V mA V V V % nA A V mV dB MHz
3V VIN 20V OC Held Low for VIN < VUVLO 3V VIN 20V
1.95 0.5955 0.5925 -150
2.2 0.6 0.6 0.02 -75 -8.5 0.93 48
VFB Line Regulation IFB IOC FB Input Bias Current Overshoot Control Charging Current OC Clamp Voltage OC Amplifier Offset Voltage AVOL Error Amplifier Open-Loop DC Gain Error Amplifier Unity-Gain Bandwidth Error Amplifier Output Swing Low Error Amplifier Output Swing High Error Amplifier Output Source Current Error Amplifier Output Sink Current Opto Driver Inverting DC Gain Opto Driver -3dB Bandwidth Opto Driver Output Swing Low Opto Driver Output Swing High
3V VIN 20V FB = VFB VOC = 0V FB = 0.3V VCOMP = 0.8V to 1V No Load (Note 4) FB = 1V FB = 0V FB = 0V, COMP = 1V FB = 1V, COMP = 1V -6.4 No Load (Note 4) FB = 0V, COMP = Open VIN = 3V, FB = 1V, COMP = Open, IOPTO = 10mA VIN = 20V, FB = 1V, COMP = Open, IOPTO = 10mA

-15
60 0.1 1.2 -800
80 9 0.35 1.33 -450 25 -6 600 0.5 0.85 -5.6 0.55 1.5 -225
VIN - 1.25 VIN - 1.05 4.2 5.6 7.5
2
U
V V A mA V/V kHz V V V
4430f
W
U
U
WW
W
LT4430 ELECTRICAL CHARACTERISTICS
SYMBOL ISC PARAMETER Opto Driver Output Short-Circuit Current (Sourcing) Opto Driver Output Sink Current FB = 0V, OPTO = 1.5V
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 5V, FB = VFB, COMP = 1V, unless otherwise noted (Note 3).
CONDITIONS FB = 1V, COMP = Open, OPTO = 0V
MIN 10.5 150
TYP 22 350
MAX 45 650
UNITS mA A
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT4430 is guaranteed to meet performance specifications from 0C to 125C. Specifications over the -40C to 125C operating temperature range are assured by design, characterization and correlation with statistical process controls.
Note 3: All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 4: This parameter is guaranteed by correlation and is not tested.
TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current vs Temperature
4.0 3.5 QUIESCENT CURRENT (mA) 2.5 3.0 2.5 2.0 1.5 1.0 -50 -25 1.0 -50 -25 VIN = 3V 2.0 VFB (V) VIN = 20V VUVLO (V) 3.0
0
25 50 75 100 125 150 TEMPERATURE (C)
4430 G01
FB Voltage Line Regulation
0.6010 TA = 25C FB INPUT BIAS CURRENT (nA) 50 25 0.6005 0 -25 -50 -75 -100 -125 -150 -175 0.5990 0 2 4 6 8 10 12 14 16 18 20 VIN (V)
4430 G04
VFB (V)
0.6000
0.5995
UW
Undervoltage Lockout Threshold vs Temperature
0.606 0.605 0.604 0.603 0.602 0.601 0.600 0.599 0.598 1.5 0.597 0.596 0.595 0 25 50 75 100 125 150 TEMPERATURE (C)
4430 G02
Feedback Reference Voltage vs Temperature
0.594 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
4430 G03
FB Input Bias Current vs Temperature
-200 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
4430 G07
4430f
3
LT4430 TYPICAL PERFOR A CE CHARACTERISTICS
OC Charging Current vs Input Voltage
15 15
OC CHARGING CURRENT (A)
OC CHARGING CURRENT (A)
13
11
OC CLAMP VOLTAGE (V)
9
7
5 0 5 10 VIN (V) 15 20
4430 G08
OC Amplifier Offset Voltage vs Temperature
100 90 80 VOC - VFB (mV) 70 GAIN (dB) 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
4430 G11
70 60 50 40 30 20 10 0 -10 -20 1k 10k 1M 100k FREQUENCY (Hz) 10M -45 50M 0 GAIN 45 PHASE 90 PHASE () 135
ERROR AMPLIFIER OUTPUT SWING LOW (V)
ERROR AMPLIFIER OUTPUT SOURCE CURRENT (A)
Error Amplifier Output Swing High vs Temperature
ERROR AMPLIFIER OUTPUT SWING HIGH (V) 1.5
1.4
1.3
1.2
1.1
1.0 -50 -25
4
UW
0
OC Charging Current vs Temperature
VIN = 5V 1.5
OC Clamp Voltage vs Temperature
13
1.3
11
1.1
9
0.9
7
0.7
5 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
4430 G09
0.5 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
4430 G10
Error Amplifier Open Loop Gain and Phase vs Frequency
80 180 0.5
Error Amplifier Output Swing Low vs Temperature
0.4
0.3
0.2
0.1
0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
4430 G13
4430 G12
Error Amplifier Output Source Current vs Temperature
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
4430 G16
25 50 75 100 125 150 TEMPERATURE (C)
4430 G14
4430f
LT4430 TYPICAL PERFOR A CE CHARACTERISTICS
Error Amplifier Output Sink Current vs Temperature
ERROR AMPLIFIER OUTPUT SINK CURRENT (mA) 50 OPTO DRIVER INVERTING DC GAIN (V/V) 6.4 6.3 6.2 GAIN (dB) 6.1 6.0 5.9 5.8 5.7 5.6 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
4430 G17
40
30
20
10
0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
4430 G15
Opto Driver Output Swing Low vs Temperature
1.0 OPTO DRIVER OUTPUT SWING LOW (V) 0.9 0.8 VIN - VOPTO (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
4430 G19
OPTO DRIVER OUTPUT SWING HIGH (V)
Opto Driver Output Sink Current vs Temperature
900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
4430 G23
OPTO DRIVER SHORT-CIRCUIT CURRENT (mA)
OPTO DRIVER OUTPUT SINK CURRENT (A)
1000
UW
Opto Driver Inverting DC Gain vs Temperature
40 35 30 25 20 15 10 5 0 -5 -10
Opto Driver Inverting Closed Loop Gain and Phase vs Frequency
180 PHASE 135
90 GAIN 45
PHASE ()
0
1k
10k
1M 100k FREQUENCY (Hz)
-45 10M
4430 G18
Opto Driver Output Swing High vs Temperature
1.5 VIN = 3V 1.4 IOPTO = 10mA 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
4430 G20
Opto Driver Output Swing High vs Temperature
8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
4430 G21
VIN = 20V IOPTO = 10mA
Opto Driver Output Short-Circuit Current (Sourcing) vs Temperature
40
30
20
10
0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
4430 G22
4430f
5
LT4430 PI FU CTIO S
VIN (Pin 1): This is the input supply that powers all internal circuitry. The input supply range is 3V minimum to 20V maximum and the typical input quiescent current is 1.9mA. Connect a 1F bypass capacitor directly from VIN to GND. GND (Pin 2): Analog Ground Pin. It is also the negative sense terminal for the internal 0.6V reference. Connect the external feedback divider network that terminates to ground directly to this pin for best regulation and performance. OC (Pin 3): Overshoot Control Pin. A typical 8.5A current source and a capacitor placed from this pin to GND controls output voltage overshoot on startup and recovery from short-circuit. The typical ramp time is (COC * 0.6V)/8.5A. If VIN is below VUVLO (its undervoltage lockout threshold), the OC pin is actively held low. The OC pin also ties to the overshoot control amplifier output. This amplifier monitors the FB pin voltage and the error amplifier output. If FB is low due to a short-circuit fault condition, the COMP pin goes high. Logic detects the error amplifier COMP pin high state and activates the overshoot control amplifier. The amplifier responds by discharging the OC capacitor down to the FB voltage plus a built-in offset voltage of 48mV. If the short-circuit condition persists, the amplifier maintains the voltage on OC. If the short-circuit condition goes away, the FB pin recovers under the control of the OC pin. FB (Pin 4): This is the inverting input of the error amplifier. The non-inverting input is tied to the internal 0.6V reference. Input bias current for this pin is typically 75nA flowing out of the pin. This pin normally ties to a resistor divider network to set output voltage. Tie the top of the external resistor divider directly to the output voltage for best regulation performance. COMP (Pin 5): This is the output of the error amplifier. The error amplifier is a true voltage-mode error amplifier and frequency compensation is performed around the amplifier. Typical LT4430 compensation schemes use series R-C in parallel with C networks from the COMP pin to the FB pin. COMP also ties to the overshoot control amplifier logic that detects if the COMP pin is at its high clamp level. The logic activates the overshoot control amplifier if COMP is at its clamp level for longer than 1s. OPTO (Pin 6): This is the output of the amplifier that drives the optocoupler. The opto driver amplifier uses an inverting gain of six configuration to drive the optocoupler referenced to ground. Driving the optocoupler referenced to GND accommodates low output voltages and eases loop frequency compensation as the secondary feedback path with a traditional "431" topology is eliminated. The opto driver amplifier sources a maximum of 10mA, sinks 350A typically and is short-circuit protected.
6
U
U
U
4430f
LT4430 BLOCK DIAGRA W
VIN I1 12.5A BIAS AND REFERENCE GENERATOR 1.1V 0.6V Q2 Q3 COMP
+
OPTO DRIVER OUT
+
ERROR AMP
-
R3 15k R4 90k
VIN
STARTUP
-
VIN I2 12.5A UVLO Q1 VIN R1 2k FB DFB Q5 V1 0.2V IOC 8.5A LOGIC AND DELAY Q7 GND
+ -
V2 0.6V
Q4
Q6 S1 NORMALLY OPEN OC
OC AMP
+ -
APPLICATIO S I FOR ATIO
Block Diagram Operation
A precision voltage reference, a high-bandwidth error amplifier, an inverting optocoupler driver and an overshoot control amplifier comprise the LT4430. Referring to the block diagram, a start-up circuit establishes all internal current and voltage biasing for the IC. A precision-trimmed bandgap generates the 600mV reference voltage and a 1.1V bias voltage for the optocoupler driver. Room temperature reference voltage accuracy is specified at 0.75% and operating temperature range tolerance is specified at 1.25%. The 600mV reference ties to the non-inverting input of the error amplifier. The LT4430 error amplifier senses the output voltage through an external resistor divider and regulates the FB pin to 600mV. The FB pin ties to the inverting input of the error amplifier. The error amplifier's open loop DC gain is 80dB and its unity-gain crossover frequency of 9MHz provides negligible phase shift at typical feedback loop crossover frequencies. The error amplifier is a true
voltage-mode amplifier and frequency compensation connects around the amplifier. Typical LT4430 compensation schemes use series R-C in parallel with C networks from the COMP pin to the FB pin. The optocoupler driver amplifies the voltage difference between the COMP pin and the 1.1V bias potential applied to its non-inverting terminal with an inverting gain of 6. This signal drives the optocoupler referenced to GND. Driving the optocoupler referenced to GND accommodates low output voltages and simplifies loop frequency compensation as the secondary feedback path with a traditional "431" topology is eliminated. A resistor in series with the optocoupler sets the optocoupler's DC bias current. The opto driver amplifier sources a guaranteed maximum of 10mA, sinks 350A typically and is short-circuit protected. The optocoupler driver amplifier's typical -3dB bandwidth is 600kHz. The optocoupler's output crosses the galvanic isolation barrier and closes the feedback loop to the primary-side controller.
4430f
- + + -
VOS 48mV
4430 BD01
R2 2k
U
W
U
U
7
LT4430 APPLICATIO S I FOR ATIO
The LT4430 incorporates a unique overshoot control function that allows the user to ramp the output voltage on startup and recovery from short-circuit conditions, preventing overshoot. A capacitor, connected from the OC pin to GND and charged by internal 8.5A current source IOC, sets the ramp rate. On startup, Q1 actively holds the OC capacitor low until VIN of the LT4430 reaches its typical undervoltage lockout threshold of 2.2V. Q1 then turns off and the OC capacitor charges linearly. Q2 and Q3 OR the OC pin voltage and the 600mV reference voltage at the non-inverting terminal of the error amplifier. The OC pin voltage is the reference voltage for the error amplifier until it increases above 600mV. If the feedback loop is in control, the FB pin voltage follows and regulates to the OC pin voltage. As the OC pin voltage increases past 600mV, the reference voltage takes control of the error amplifier and the FB pin regulates to 600mV. The OC pin voltage increases until it is internally clamped by R2, Q6 and V1. The OC pin's typical clamp voltage of 0.93V ensures that Q3 turns off. All of I1's current flows in Q2, matching I2's current in Q4. In a short-circuit condition, the output voltage decreases to something well below the regulated level. The error amplifier reacts by increasing the COMP pin voltage, thereby decreasing the drive to the optocoupler. The decreased optocoupler bias signals the primary-side controller to increase the amount of power it delivers in an attempt to raise the output voltage back to its regulated value. As long as the fault persists, the output voltage remains low. The error amplifier's COMP pin voltage increases until it reaches a clamp level set by Q7 and V2. Q7's resultant collector current drives internal logic that closes normally open switch S1. This action activates the overshoot control amplifier which employs a unity-gain follower configuration. The overshoot control amplifier monitors the FB pin voltage and, on S1's closing, pulls the OC pin voltage down to the FB pin voltage plus a built-in offset voltage of typically 48mV. The built-in offset voltage serves two
8
U
purposes. First, the offset voltage prevents the overshoot control amplifier from interfering with normal transient operating conditions. Second, the offset voltage biases the feedback loop so that if the short-circuit condition ends, the feedback loop immediately starts to increase the output voltage to its regulated value. If the fault condition ceases, the output voltage increases. In response, the error amplifier COMP pin's voltage decreases. This action opens switch S1, deactivates the overshoot control amplifier and allows the OC pin capacitor to charge. The FB pin voltage increases quickly until the FB pin voltage exceeds the OC pin voltage. The feedback loop increases the drive to the optocoupler until the FB pin follows and regulates to the OC pin voltage. Again, as the OC pin voltage increases past 600mV, the reference voltage takes control of the error amplifier and the FB pin regulates to 600mV. Generating a VIN Bias Supply Biasing an LT4430 is crucial to proper operation. If the overshoot control (OC) function is not being used and the output voltage is greater than 3.3V, the IC may be biased from VOUT. In these cases, it is the user's responsibility to verify large-signal startup and fault recovery behavior. If the overshoot control function is being used or the output voltage is below the LT4430's minimum operating voltage of 3V, employing an alternate bias method is necessary. The LT4430's undervoltage lockout (UVLO) circuitry, controlled by VIN, resets and holds the OC pin capacitor low for VIN less than 2.2V. When VIN increases above 2.2V, the circuit releases the OC pin capacitor. The LT4430's supply voltage must come up faster than the ouput voltage to assert loop control and limit output voltage overshoot. In most cases, a few simple components accomplish this task. Adding a few biasing components to control overshoot is advantageous. Let's examine bias circuits for different topologies.
4430f
W
U
U
LT4430 APPLICATIO S I FOR ATIO
Figures 1a to 1e illustrate bias supply circuits for the flyback converter. Figure 1a shows the typical flyback output connection. Figures 1b and 1c exhibit equivalent circuit performance but rotate the rectifier connection to the ground-referred side. This connection permits the user to take advantage of the transformer secondary's forward behavior when the primary-side switch is on. Figures 1d to 1e illustrate the bias generator circuit. VIN * N volts appear across the secondary winding when the primary-side switch is on. D2 forward biases and C1 charges. During this time, the secondary-voltage is in series with VOUT and C1 ultimately charges to (VIN * N + VOUT - VF). VF is the forward voltage of D2. When VOUT is zero at startup, VIN * N volts exists to charge C1. C1 is generally much smaller in value than COUT and the bias supply starts up ahead of VOUT. R1 in Figures 1d and 1e limits peak charging currents, lowering D2's current rating. R1 also filters C1 from peak-charging to the voltage spikes induced by the secondary winding's leakage inductance. Between 1 to 10 is generally sufficient. R1 is usually necessary if C1 is a low ESR ceramic capacitor or if the transformer has high leakage inductance. It may be possible to eliminate R1 if C1 is a low cost, high ESR, surface-mount tantalum.
T1 VIN T1 VOUT D1 COUT VIN
* *
1:N
4430 F01a
Figure 1a. Typical Flyback Converter Connection
Figure 1b. Equivalent Flyback Converter Connection
T1
T1 VIN
* *
1:N D1
VOUT COUT 1:N
D2 *OPTIONAL SEE TEXT
R1*
LT4430 VBIAS C1
4430 F01d
Figure 1d. Flyback Converter with Bias Generator
U
VIN variation changes the bias supply in Figure 1d. Depending on VOUT, the transformer turns ratio N and VIN range, the bias supply may exceed the LT4430's 20V VIN absolute maximum rating. If this occurs, two solutions exist. One is to tap the secondary-side inductor to create a lower voltage from which to rectify as illustrated in Figure 2a. The bias voltage decreases to (VIN * N1/N + VOUT - VF). This solution relies on secondary-side pins being available for the tap point. The second solution is to make a preregulator as shown in Figure 2b. In this example, the bias supply equals (VZ1 - VBE). Select R2 to bias zener diode Z1 and to supply base current to QBS. Resistor R3 (on the order of a few hundred ohms), in series with Q5's base, suppresses possible high frequency oscillations depending on QBS's selection. The preregulator circuit has additional value for fully synchronous converters. Fully synchronous converters require gate drivers to control the secondary-side MOSFETs turn on and turnoff. The gate driver circuitry requires supply current in the range of 10mA to 100mA depending on the gate driver supply voltage, MOSFET size and switching frequency. The preregulator bias supply is ideal for powering both the LT4430 and the gate driver
T1 VIN VOUT COUT
W
U
U
* *
1:N Q1
VOUT COUT
* *
1:N D1
SYNC
4430 F01b 4430 F01c
Figure 1c. Synchronous Flyback Converter Connection
VIN
* *
Q1
VOUT COUT
SYNC LT4430 VBIAS C1
4430 F01e
D2 *OPTIONAL SEE TEXT
R1*
Figure 1e. Synchronous Flyback with Bias Generator
4430f
9
LT4430 APPLICATIO S I FOR ATIO
circuitry, especially since the gate drivers typically use a supply voltage between 5V to 12V. The preregulator circuit finds wide use in fully synchronous forward converters, push-pull converters and full-bridge converters. Generate a bias supply for a forward converter using similar techniques to that of the flyback converter. Figure 3a to 3c detail the three common bias circuits for the synchronous
T1 VOUT N1 VIN VIN
*
*
COUT 1:N
N2
*
1:N N = N1 + N2 *OPTIONAL SEE TEXT
D1 C1 LT4430 VBIAS C1
4430 F02a
D2
R1*
Figure 2a. Flyback Converter with Tapped Secondary Bias
VIN
*
Figure 3a. Typical Single-Switch Synchronous Forward Converter with Bias Generator
LT4430 VBIAS C1
D1 T1
R1*
*
N2 VIN
L1
VOUT COUT
*
T1
*
N1
1:N Q1 N = N1 + N2
FG Q2
CG *OPTIONAL SEE TEXT
4430 F03b
Figure 3b. Single-Switch Synchronous Forward Converter with Tapped Secondary Bias Generator
10
U
single-switch forward converter. In the flyback converter of Figure 1d, the bias supply is proportional to VIN and VOUT. However, in the forward converter, L1's presence decouples the bias supply from VOUT. In Figure 3a, the bias supply equals (VIN * N - VF). In Figure 3b, the bias supply equals (VIN * N1/N - VF). In Figure 3c, the bias supply equals (VZ1 - VF).
T1
W
U
U
* *
D1
VOUT COUT
D2
R1*
R2 QBS R3* Z1 C2 LT4430 VBIAS
*OPTIONAL SEE TEXT
4430 F02b
Figure 2b. Flyback Converter with Preregulator Bias
LT4430 VBIAS C1
D1 T1
R1*
*
L1
VOUT COUT
1:N Q1
FG
Q2
CG *OPTIONAL SEE TEXT
4430 F03a
D1
R1*
R2 QBS R3* Z1 C2
C1
LT4430 VBIAS
VIN
*
*
L1
VOUT COUT
1:N Q1
FG
Q2
CG *OPTIONAL SEE TEXT
4430 F03c
Figure 3c. Single-Switch Synchronous Forward Converter with Preregulator Bias Generator
4430f
LT4430 APPLICATIO S I FOR ATIO
Figures 4a to 4d demonstrate bias supply circuits for the fully-synchronous push-pull topology. Biasing for fullbridge schemes is identical to the push-pull circuits with the obvious difference in the primary-side drive. In Figure 4a, the bias supply equals (VIN * N - VF). In Figure 4b and 4d, the bias supply equals (2 * VIN * N - VF). In Figure 4c and 4e, the bias supply equals (VZ1 - VF). In general, one of the simple, low-cost biasing schemes suffices for LT4430 applications. However, design conT1 Q2 D1 R1* LT4430 VBIAS C1
* *
VIN ME
L1
VOUT COUT
* *
1:N MF *OPTIONAL SEE TEXT Q1
4430 F04a
Figure 4a. Typical Synchronous Push-Pull Converter with Bias Generator
D1
R1*
R2 QBS R3* Z1 C2
C1
LT4430 VBIAS D1 R1* LT4430 VBIAS C1 T1 L2 Q2 ME
T1
Q2
* *
VIN ME L1 VOUT COUT VIN
* *
1:N MF *OPTIONAL SEE TEXT Q1
4430 F04c
Figure 4c. Typical Synchronous Push-Pull Converter with Preregulator Bias
Figure 4d. Typical Synchronous Push-Pull Current-Doubler Converter with Bias Generator
U
straints such as a very wide input voltage range may force employment of other biasing circuits. Other methods of generating the bias supply may include an additional transformer or output inductor winding, low-cost linear regulators, discrete or monolithic charge pumps and buck/boost regulators. However, if the bias supply gets this complicated, a quick chat with your local LTC applications engineer may result in a simpler solution.
T1 Q2 D1 R1* LT4430 VBIAS C1
W
U
U
* *
VIN ME L1 VOUT COUT
* *
1:N MF *OPTIONAL SEE TEXT Q1
4430 F04b
Figure 4b. Typical Synchronous Push-Pull Converter with 2x Bias Generator
D1
R1*
R2 QBS R3* Z1 C2
C1
LT4430 VBIAS
T1
* *
*
Q2 ME
L2
*
VOUT VIN VOUT COUT
* *
1:N L1 Q1 MF
* *
1:N L1 Q1 MF
COUT
*OPTIONAL SEE TEXT
4430 F04d
*OPTIONAL SEE TEXT
4430 F04e
Figure 4e. Typical Synchronous Push-Pull Current-Doubler Converter with Preregulator Bias
4430f
11
LT4430 APPLICATIO S I FOR ATIO
Setting Output Voltage Figure 5 shows how to program the power supply output voltage with a resistor divider feedback network. Connect the top of R1 to VOUT, the tap point of R1/R2 to FB and the bottom of R2 directly to GND of the LT4430. The FB pin regulates to 600mV and has a typical input pin bias current of 75nA flowing out of the pin. The output voltage is set by the formula: VOUT = 0.6V * (1 + R1/R2) - (75nA) * R1
VOUT 75nA FB R2
4430 F05
R1
Figure 5. Setting Output Voltage
OptoCoupler Feedback and Frequency Compensation An isolated power supply with good line and load regulation generally employs the following strategy. Sense and compare the output voltage with an accurate reference potential. Amplify and feed back the error signal to the supply's control circuitry to correct the sensed error. Have the error signal cross the isolation barrier if the control circuitry resides on the primary-side. Coupling this signal requires an element that withstands the isolation potentials and still transfers the loop error signal. Optocouplers remain in prevalent use because of their ability to couple DC signals. Optocouplers typically consist of an input infrared light emitting diode (LED) and an output phototransistor separated by an insulating gap.
ISOLATION BARRIER PRIMARY-SIDE ERROR AMP RC VREF FB VCC OPTO RK CK
+ -
VC
CC
Figure 6a. Frequency Compensation with Optocoupler Common-Emitter Configuration
12
U
Most optocoupler datasheets loosely specify the gain, or current transfer ratio (CTR), between the input diode and the output transistor. CTR is a strong function of the input diode current, temperature and time (aging). Aging degrades the LED's brightness and accelerates with higher operating current. CTR variation directly affects the overall system loop gain and the design must account for total variation. To make an effective optical detector, the output transistor design maximizes the base area to collect light energy. This constraint yields a transistor with a large collector-to-base capacitance. This capacitance can influence the circuit's performance based on the output transistor's hookup. The two most common topologies for the output transistor of the optocoupler are the common-emitter and common-collector configurations. Figure 6a illustrates the common-emitter design with the output transistor's collector connected to the output of the primary-side controller's error amplifier. In this example, the error amplifier is typically a transconductance amplifier with high output impedance and RC dominates the impedance at the VC node. Frequency compensation for this feedback loop is directly affected by the output transistor's collector-to-base capacitance as it introduces a pole into the feedback loop. This pole varies considerably with the transistor's operating conditions. In many cases, this pole limits the achievable loop bandwidth. Cascoding the output transistor significantly reduces the effects of this capacitance and increases achievable loop bandwidth. However, not all designs have the voltage headroom required for the cascode connection or can tolerate the additional circuit complexity. The open loop transfer function from the output voltage to the primaryLT4430 VOUT
W
U
U
+
OPTO DRIVER
1.1V
+
R4 15k ERROR AMP COMP
0.6V R1 FB C1
-
R5 90k
-
R2 C3 C2
4430 F06a
OPTO
R3
4430f
LT4430 APPLICATIO S I FOR ATIO
side error amplifier's output is:
VC VOUT R2 -A * * (1 + s * R1* C1)* (1 + s * R3 * C 3) R1 + R2 = * (C 2 * C 3) [s * A * R1* (C 2 + C 3)]* 1 + s * R3 * (C 2 + C 3) CTR * RC (1 + s * RK * C K ) * * 6* (RK + RD ) (RK * RD ) * CK 1+ s * (RK + RD ) 1 * (CTR * RC ) 1 + s * r * (R + R ) * C CB + C BE D K 1 (1+ s * RC * C C )
where: A = LT4430 open loop DC Gain RD = Optocoupler diode equivalent small-signal resistance CTR = Optocoupler AC current transfer ratio CCB = Optocoupler non-linear collector-to-base capacitor CBE = Optocoupler non-linear base-to-emitter capacitor r = Optocoupler small-signal base-to-emitter resistor Figure 6a and its transfer function illustrate most of the possible poles and zeroes that can be set and are shown for the sake of completeness. In a practical application, the transfer function simplifies considerably because not all
ISOLATION BARRIER PRIMARY-SIDE ERROR AMP VCC VREF FB OPTO RK CK OPTO
VC
+ -
RC CC RE C2
4430 F06b
Figure 6b. Frequency Compensation with Optocoupler Common-Collector Configuration
4430f
U
the poles and zeroes are used. Also, different combinations of poles and zeroes can result in the same small signal gain-phase characteristics but demonstrate dramatically different large-signal behavior. The common-collector configuration eliminates the miller effect of the output transistor's collector-to-base capacitance and generally increases achievable loop bandwidth. Figure 6b illustrates the common-collector design with the output transistor's emitter connected to the inverting input of the primary-side controller's error amplifier. In this example, the error amplifier is typically a voltage error amplifier configured as a transimpedance amplifier. The optocoupler transistor's emitter provides feedback information directly to the FB pin and the resistor RE from FB to GND sets the DC bias condition for the optocoupler. The open loop transfer function from the output voltage to the primary-side error amplifier's output is:
VC VOUT R2 -A * * (1 + s * R1* C1)* (1 + s * R3 * C 3) R1 + R2 = * (C 2 * C 3) [s * A * R1* (C 2 + C 3)]* 1 + s * R3 * (C 2 + C 3) CTR * RC (1 + s * RK * C K ) * * 6* (RK + RD ) (RK * RD ) * CK 1+ s * (RK + RD ) 1 1 * (1+ s * r * C BE ) (1+ s * RC * C C )
W
U
U
Figure 6b and its transfer function illustrate most of the possible poles and zeroes that can be set and are shown for the sake of completeness. In a practical application, the transfer function simplifies considerably because not all the poles and zeroes are used.
LT4430 VOUT
+
OPTO DRIVER
1.1V
+
R4 15k ERROR AMP COMP
0.6V R1 FB C1
-
R5 90k C3
-
R2 R3
13
LT4430 APPLICATIO S I FOR ATIO
In both configurations, the terms RD, CTR, r, CCB and CBE. vary from part to part and also change with bias current. For most optocouplers, RD is 50 at a DC bias of 1mA, and 25 at a DC bias of 2mA. CTR is the small signal AC current transfer ratio. As an example, the Fairchild MOC207 optocoupler has an AC CTR around 1, even though the DC CTR is much lower when biased at 1mA or 2mA. Most optocoupler datasheets do not specify the terms CCB, CBE and r and values must be obtained from empirical measurements. This frequency compensation discussion only addresses the transfer function from the output back to the control node on the primary-side. Compensation of the entire feedback loop must combine this transfer function with the transfer function of the power processing circuitry, commonly referred to as the modulator. In an isolated power supply, the modulator's transfer function depends on topology (flyback, forward, push-pull, bridge), current or voltage mode control, operation in discontinuous or continuous mode, input/output voltage, transformer turns ratio and output load current. It is beyond this datasheet's scope to detail the transfer functions for all of the various combinations. However, the power supply designer must fully characterize and understand the modulator's transfer function to successfully frequency compensate the feedback loop for all operating conditions. OptoCouplers Optocouplers are available in a wide variety of package styles and performance criteria including isolation rating, CTR, output transistor breakdown voltage, output transistor current capability, and response time. Table 1 lists several manufacturers of optocoupler devices, although this is by no means a complete list.
Table 1. Optocoupler Vendors
VENDOR Agilent Technologies Fairchild Semiconductor Isocom Kodenshi Korea Corp. NEC Sharp Microelectronics Toshiba Vishay PHONE 800-235-0312 207-775-8100 214-495-0755 82-63-839-2111 81-44-435-1588 877-343-2181 949-455-2000 402-563-6866 URL www.agilent.com www.fairchildsemi.com www.isocom.com www.kodenshi.co.kr www.ncsd.necel.com www.sharpsma.com
4430 F07
www.toshiba.com www.vishay.com
14
U
Setting Overshoot Control Time Figure 7 shows how to calculate the overshoot time by connecting a capacitor from the OC pin to GND. The overshoot control time, tOC, is set by the formula: tOC = (COC * 0.6V)/8.5A The OC pin requires a minimum capacitor of 100pF due to stability requirements with the overshoot control amplifier. This yields a minimum time of 7s which is generally on the order of a few cycles of the switching regulator. Using the minimum capacitor value results in no influence on startup characteristics. Larger OC capacitor values increase the overshoot control time and only increase the amplifier stability. Do not modulate the overshoot control time by externally increasing the OC charging current or by externally driving the OC pin. Choosing the Overshoot Control (OC) Capacitor Value As discussed in the frequency compensation section, the designer enjoys considerable freedom in setting the feedback loop's pole and zero locations for stability. Different pole and zero combinations can produce the same gain-phase characteristics, but result in noticeably different large-signal responses. Choosing frequency compensation values that optimize both small-signal and large-signal responses is difficult. Compromise values often result. Power supply startup and short-circuit recovery are the worst-case large signal conditions. Input voltage and output load characteristics heavily influence power supply behavior as it attempts to bring the output voltage into regulation. Frequency compensation values that provide stable response under normal operating conditions can allow severe output voltage overshoot to occur during startup and short-circuit recovery conditions. Large overshoot often results in damage or destruction to the load circuitry being powered, not a desirable trait.
VIN IOC 8.5A OC COC
W
U
U
Figure 7. Setting Overshoot Control Time
4430f
LT4430 APPLICATIO S I FOR ATIO
The LT4430's overshoot control circuitry plus one external capacitor (COC) provide independent control of startup and short-circuit recovery response without compromising small-signal frequency compensation. Choosing the optimum COC value is a straightforward laboratory procedure. The following description and set of pictures explain this procedure. Before choosing a value for the OC pin capacitor, complete the remainder of the power supply design. This process includes evaluating the chosen VIN bias generator topology (please consult prior applications information section) and optimizing frequency compensation under all normal operating conditions. During this design phase, set COC to its minimum value of 100pF. This ensures negligible interaction from the overshoot control circuitry. Once these steps are complete, construct a test setup that monitors startup and short-circuit recovery waveforms. Perform this testing with the output lightly loaded. Light load, following full slew operation, is the worst-case as the feedback loop transitions from full to minimal power delivery. As an example, refer to the schematic on the last page illustrating the 5V, 2A isolated flyback converter. All of the following photos are taken with VIN = 48V and ILD = 20mA. Figure 8a demonstrates the power supply startup and short-circuit recovery behavior with no overshoot control compensation (COC = 100pF minimum). The 5V output overshoots by several volts on both startup and short-circuit recovery due to the conservative nature of the small-signal frequency compensation values. Next, increase COC's value. Either use a capacitor substitution box or solder each new value into the circuit. Monitor the startup and short-circuit recovery waveforms. Note any changes. Figures 8b to 8e illustrate what happens as COC increases. In general, overshoot decreases as COC increases. COC = 0.0168F in Figure 8b begins to affect loop dynamics, but startup still exhibits about 1.5V of overshoot. Short-circuit recovery is considerably more damped. COC = 0.022F in Figure 8c damps startup overshoot to 0.5V and short-circuit recovery remains similar to that of Figure 8b. COC = 0.033F in Figure 8d provides under 100mV of overshoot and short-circuit recovery is slightly more damped. COC = 0.047F in Figure 8e achieves zero over-
U
shoot at the expense of additional damping and delay time in short-circuit recovery. In this example, COC = 0.033F provides the best value for both startup and short-circuit recovery. Figure 8f provides an expanded scale of the waveforms. After a COC value is selected, check startup and short-circuit recovery over the VIN supply range and with higher output load conditions. Modify the value as necessary. Startup and short-circuit recovery waveforms for various designs will differ from the photos shown in this example. Factors affecting these waveforms include the isolated topology chosen, the primary-side and secondary-side bias circuitry and input/output conditions. For instance, in many isolated power supplies, a winding on the main power transformer bootstraps the supply voltage for the primary-side control circuitry. Under short-circuit conditions, the primary-side control circuitry's supply voltage collapses, generating a restart cycle. Recovery from short-circuit is therefore identical to startup. In the flyback example discussed, the primary-side control circuitry is always active. Switching never stops in short-circuit. The LT4430 error amplifier COMP pin changes from its low clamp level to its higher regulating value during startup and changes from its high clamp level to its lower regulating point during short-circuit recovery. This large-signal behavior explains the observed difference in the startup versus short-circuit recovery waveforms. A final point of discussion involves the chosen COC value. LTC recommends that the designer use a value that controls overshoot to the acceptable level, but is not made overly large. The temptation arises to use the overshoot control function as a power supply "soft-start" feature. Larger values of COC, above what is required to control overshoot, do result in smaller dV/dt rates and longer startup times. However, large values of COC may stall the feedback loop during startup or short-circuit recovery, resulting in an extended period of time that the output voltage "flatspots". This voltage shelf may occur at an intermediate value of output voltage, promoting anomalous behavior with the powered load circuitry. If this situation occurs with the desired COC value, solutions may require circuit modifications. In particular, bias supply holdup times are a prime point of concern as switching stops during these output voltage flatspots. As a reminder,
4430f
W
U
U
15
LT4430 APPLICATIO S I FOR ATIO
the purpose of this LT4430 circuitry is to control and prevent excessive output voltage overshoot that would otherwise induce damage or destruction, not to control power supply timing, sequencing, etc. It is ultimately the
STARTUP VOUT 5V/DIV
SHORT-CIRCUIT RECOVERY VOUT 5V/DIV
t = 5ms/DIV COC = 100pF
4430 F08a
Figure 8a. Startup and Short-Circuit Recovery Waveforms
STARTUP VOUT 5V/DIV
SHORT-CIRCUIT RECOVERY VOUT 5V/DIV
t = 5ms/DIV COC = 0.022F
4430 F08c
Figure 8c. Startup and Short-Circuit Recovery Waveforms
STARTUP VOUT 5V/DIV
SHORT-CIRCUIT RECOVERY VOUT 5V/DIV
t = 5ms/DIV COC = 0.047F
4430 F08e
Figure 8e. Startup and Short-Circuit Recovery Waveforms
16
U
user's responsibility to define the acceptance criteria for any waveforms generated by the power supply relative to overall system requirements.
STARTUP VOUT 5V/DIV SHORT-CIRCUIT RECOVERY VOUT 5V/DIV t = 5ms/DIV COC = 0.0168F = 0.01F + 6.8nF
4430 F08b
W
U
U
Figure 8b. Startup and Short-Circuit Recovery Waveforms
STARTUP VOUT 5V/DIV
SHORT-CIRCUIT RECOVERY VOUT 5V/DIV
t = 5ms/DIV COC = 0.033F
4430 F08d
Figure 8d. Startup and Short-Circuit Recovery Waveforms
STARTUP VOUT 5V/DIV
SHORT-CIRCUIT RECOVERY VOUT 5V/DIV
t = 5ms/DIV COC = 0.033F
4430 F08f
Figure 8f. Zoom In of Waveforms with Selected COC = 0.033F
4430f
200W, 26V, 95% Efficient Base Station Converter
ISOLATION BARRIER Q3 BCX55 VBS D7 8.2V C10 1F R1 82k Q1 BCX55 C2 1F 2 4 L1 10H PA0741 T1 VU1 D2 18V D3 BAS516 D5 B0540W R2 47k R26 10 C9 10nF 100V
R15 2.2 C8 6.8nF 100V D6 B0540W R16 1k
36V TO 72V VIN
C1 2.2F 100V D1 12V
* * 7, 10 *
8, 11 26V 8A COUT 22F 50V X7R
TYPICAL APPLICATIO S U
R24 26.1k 1% R20 15k C12 1nF C16 10pF C15 R23 2.2nF 8.2k R25 6.04k 1%
4430 TA03a
2 4 SD_VSEC SOUT 14 15 8 13 R12 39k VBS 4 C11 1F R14 0.008 T2 C7 220pF 6 VCC 12 11 R13 680 10 5 FG CG CS+ C3 2.2F D4 BAT760 3 1 R19 10k GND SYNC 8 R21 330 CS- CS TIMER 2 7 C4 1nF VU1 R17 10k VIN GND ROSC BLANK SS_MAXDC PGND LT1952 VREF DELAY COMP FB SYNC 16 SOUT ISENSE OC Q4 PH20100 Q5 PH20100
R4 13.2k Q2 PH21NQ15 x2
R3 370k
R5 114k
7
R6 33k
3
C5 0.47F
9
R7 33k
R8 33k
5
R18 10k
6
LTC3900
VBS
C6 0.1F
R9 33k
1
2
NC
* *
4
VU1
R22 330 NEC PS2701
VBS C13 1F C14 33nF
1
VIN
OPTO LT4430 2 3 GND OC COMP FB
COUT = TDK D1, D2, D7 = PHILIPS Q1, Q2 = PHILIPS L1 = PULSE ENGINEERING PB2020.103 T1 = PULSE ENGINEERING T2 = COILCRAFT Q4470-B
6
R10 22k
5 4
R11 1.2k
C17 2200pF 250V
LT4430
17
4430f
LT4430
*
B
A
*
*
*
TYPICAL APPLICATIO S
2 0.1F 5 A B VF 1.5k ISNS 12V L4 1mH D5 1 D6 866 12 CSF- 14 15 MF MF2 6 CSE+ LTC3901EGN GND PGND GND2 PGND2 8 220pF A B 6 3 SDRA CS COMP SPRG RLEB SS DPRG VREF 1 750 243k 68nF 0.47F 330pF 22nF 5 2 6 C4 2.2nF 250V OPTO 16 9 150k 270pF 33k 10k 12 14 11 6 1 5 COMP VIN LT4430ES6 GND 2 OC 22nF -VOUT
4430 TA03b
4 0.1F 1F 100V Si7370DP x2 VE 6.19k 1/4W 1% 1k 1% 6 11 CSF+ 9 SYNC 100 T2 1(1.5mH):0.5 1 4 5 CSE- 2 3 6.19k 1/4W 1% 1k 1% 866 Si7370DP x2
2
4
3
1k 1/4W
+
C1, C2 47F 16V x2 1F
12V/20A
97 Si7852DP Si7852DP
42VIN
96
48VIN
-VOUT 1k 1/4W VOUT 100 16 ME ME2 VCC 1 PVCC TIMER 4 10 13 7 470pF VOUT 1.1k 10 MOC207 1 15nF 1.5k 4 FB 3 604 1% 11.5k 1% 4.7nF 470pF -VOUT 1F 1F MMBT3904 D7 10V 42.2k 1k
56VIN R1 0.03 1.5W C3 68F 20V R2 0.03 1.5W
EFFICIENCY (%)
95
+
94
93
6 0.1F 22 8 5
8 20
10 12 14 16 LOAD CURRENT (A)
18
VIN ISNS
12V
200 1/4W 4 DRVB SDRB LTC3723EGN-1 UVLO FB GND CT 13 7 8 2 DRVA 5 VCC
30k 1/4W
464k
15
1.5nF
1F
66.5k
*
1F, 100V TDK C3225X7R2A105M C1, C2: SANYO 16TQC47M C3: AVX TPSE686M020R0150 C4: MURATA GHM3045X7R222K-GC D1: DIODES INC. ES1B D3-D6: BAS21 D7: MMBZ5240B L4: COILCRAFT DO1608C-105 L5: COILCRAFT DO1813P-561HC L6: PULSE PA1294.132 OR PANASONIC ETQP1H1R0BFA R1, R2: IRC LRC2512-R03G T1: PULSE PA0805.004 T2: PULSE PA0785
U
VCC 6 INP BOOST LTC4440ES6 5 4.7 TG GND TS 3 VF D1 2 11 9 7 Si7852DP Si7852DP 4
VCC 6 INP BOOST LTC4440ES6 5 4.7 TG GND TS
*
18
LTC3723-1 240W 42VIN to 56VIN to 12V/20A Isolated 1/4 Brick (2.3" x 1.45")
VF D4 1 L6 1.25H VOUT T1 4T:6T(65HMIN):6T:2T:2T VE VE 12V D3 1nF 100V 10 1W
L5 0.56H
VIN
+VIN
42V TO 56V
1F 100V
-VIN
1F 100V x3
12V
1
3
*
*
4430f
LT4430 PACKAGE DESCRIPTIO U
S6 Package 6-Lead Plastic SOT-23
(Reference LTC DWG # 05-08-1634)
0.62 MAX 0.95 REF 2.80 - 3.10 (NOTE 4) 1.22 REF 1.4 MIN 2.60 - 3.00 1.50 - 1.75 (NOTE 4) PIN ONE ID 0.95 BSC 0.25 - 0.50 TYP 6 PLCS NOTE 3 0.90 - 1.30 0.20 BSC 0.90 - 1.45 DATUM `A' 0.09 - 0.20 (NOTE 3) 1.90 BSC 0.09 - 0.15 NOTE 3
S6 SOT-23 0502
3.85 MAX 2.62 REF
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.35 - 0.55 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. PACKAGE EIAJ REFERENCE IS SC-74A (EIAJ)
ATTENTION: ORIGINAL SOT23-6L PACKAGE. MOST SOT23-6L PRODUCTS CONVERTED TO THIN SOT23 PACKAGE, DRAWING # 05-08-1636 AFTER APPROXIMATELY APRIL 2001 SHIP DATE
4430f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT4430 TYPICAL APPLICATIO U
ISOLATION BARRIER 36V TO 72V VIN C1 1F 100V -VIN R1 220k D1 PDZ-9.1B 9.1V R2 100k CTX-02-15242 T1 2 4 Q1 FDC2512 5V 2A 8.5V D2 BAS516
5V, 2A Isolated Flyback Telecom Converter Startup Waveforms with and without Overshoot Control Implemented
Q2 MMBTA42
*
9, 10
* 11, 12
D4 UPS840
CO1 100F 6.3V
CO2 100F 6.3V
CO3 100F 6.3V
ITH/SHDN
ITH/RUN GND FB LTC3803
NGATE VCC SENSE R3 4.7k C2 1F 10V
R4 220
C3 150pF 200V RCS 0.068 8.5V R5 6.8k
D5 MBR0530
R7 11k 1%
R10 680
C8 0.047F
C5 1F C6 0.033F
VIN GND OC LT4430
C7 OPTO R9 0.1F 1k COMP FB R8 1500 1%
4430 TA02
D3 BAS516 C1 = TDK, X7R CO1, C02, C03 = TDK, X5R D1, D2, D3 = PHILIPS D4 = MICROSEMI Q1 = FAIRCHILD Q2 = DIODES, INC. T1 = COOPER MOC207 = FAIRCHILD R6 470k
MOC207
C4 2200pF 250V
RELATED PARTS
PART NUMBER LTC1693 LTC1698 LT1950 LT1952 LT3710 LTC3722-1/ LTC3722-2 LTC3723-1/ LTC3723-2 LT3781 LTC3803 LT3804 LTC3900 LTC3901 DESCRIPTION High Speed Single/Dual N-Channel MOSFET Drivers Isolated Secondary Synchronous Rectifier Controller Forward Controller Single-Switch Synchronous Forward Controller Secondary Side Synchronous Post Regulator Synchronous Dual Mode Phase Modulated Full-Bridge Controllers Synchronous Push-Pull PWM Controllers COMMENTS CMOS Compatible Input, VCC Range: 4.5V to 13.2V Pulse Transformer Synchronization, Optocoupler Driver Programmable Volt-Second Clamp and Slope Compensation Synchronous Output Driver, Precision Current Limit, Programmable Volt-Second Clamp and Slope Compensation Generates Regulated Auxiliary Output in Isolated DC/DC Converters, Dual N-Channel MOSFET Synchronous Drivers 50W to 2kW Power Supply Design, Adaptive Direct Sense ZVS LTC3723-1: Peak Current Mode Control, Programmable Slope Compensation, Leading Edge Blanking LTC3723-2: Voltage Mode Control with Voltage Feedforward Operation up to 72V Maximum Adjustable Slope Compensation, Internal Soft-Start, 200kHz
Dual Transistor Synchronous Forward Controller Constant Frequency Current Mode Flyback DC/DC Controller in ThinSOT
Secondary Side Dual Output Controller with Opto Driver Regulates Two Outputs, OptoCoupler Feedback Driver and Second Output Synchronous Driver Controller Synchronous Rectifier Driver for Forward Converters Synchronous Rectifier Driver for Push-Pull and FullBridge Converters Programmable Timeout, Synchronization Sequence Monitor, Reverse Inductor Current Sense Programmable Timeout, Synchronization Sequence Monitor, Reverse Inductor Current Sense
4430f
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT/TP 0804 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

▲Up To Search▲

Price & Availability of LT4430

	To Download LT4430 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .